june 2000 copyright ?2000 alliance semiconductor. all rights reserved. ? as7c4098 AS7C34098 7/21/00 alliance semiconductor 1 5v/3.3v 256k 16 cmos sram features ? as7c4098 (5v version) ? AS7C34098 (3.3v version) ? industrial and commercial temperature ? organization: 262,144 words 16 bits ? center power and ground pins ?high speed - 10/12/15/20 ns address access time - 5/6/7/9 ns output enable access time ? low power consumption: active - 1375 mw (as7c4098)/max @ 12 ns - 468 mw (AS7C34098)/max @ 12 ns ? low power consumption: standby - 110 mw (as7c4098)/max cmos - 72 mw (AS7C34098)/max cmos ? individual byte read/write controls ? 2.0v data retention ? easy memory expansion with ce , oe inputs ? ttl- and cmos-compatible, three-state i/o ? 44-pin jedec standard packages - 400-mil soj - 400-mil tsop ii ? esd protection 3 2000 volts ? latch-up current 3 200 ma logic block diagram 1024 256 16 array (4,194,304) oe ce we column decoder row decoder a0 a1 a2 a3 a4 a6 a7 a8 v cc gnd a12 a5 a9 a10 a11 a14 a15 a16 a17 a13 control circuit i/o1Ci/o8 i/o9Ci/o16 ub lb i/o buffer pin arrangement 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 i/o14 i/o13 gnd v cc i/o12 i/o11 i/o10 i/o9 nc a14 a13 a12 a11 a10 a4 ce i/o1 i/o2 i/o3 i/o4 v cc gnd i/o5 i/o6 i/o7 i/o8 we a5 a6 a7 44-pin soj, tsop ii (400 mil) 21 22 a8 a9 ub lb i/o16 i/o15 2 a1 3 a2 4 a3 1 a0 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 43 42 41 44 a16 a15 oe a17 selection guide shaded areas indicate preliminary information. AS7C34098 C10 as7c4098 AS7C34098 C12 as7c4098 AS7C34098 C15 as7c4098 AS7C34098 C20 unit maximum address access time 10 12 15 20 ns maximum output enable access time 5679ns maximum operating current as7c4098 C 250 220 180 ma AS7C34098 160 130 110 100 ma maximum cmos standby current as7c4098 C 20 20 20 ma AS7C34098 20 20 20 20 ma
? 2 alliance semiconductor 7/21/00 as7c4098 AS7C34098 functional description the as7c4098 and AS7C34098 are high-performance cmos 4,194,304-bit static random access memory (sram) devices organized as 262,144 words 16 bits. they are designed for memory applications where fast data access, low power, and simple interfacing are desired. equal address access and cycle times (t aa , t rc , t wc ) of 10/12/15/20 ns with output enable access times (t oe ) of 5/6/7/9 ns are ideal for high-performance applications. the chip enable input ce permits easy memory expansion with multiple-bank memory systems. when ce is high the device enters standby mode. the standard as7c4098 is guaranteed not to exceed 110 mw power consumption in cmos standby mode. both devices offer 2.0v data retention. a write cycle is accomplished by asserting write enable (we ) and chip enable (ce ). data on the input pins i/o1Ci/o16 is written on the rising edge of we (write cycle 1) or ce (write cycle 2). to avoid bus contention, external devices should drive i/o pins only after outputs have been disabled with output enable ( oe ) or write enable (we ). a read cycle is accomplished by asserting output enable (oe ) and chip enable (ce ), with write enable (we ) high. the chip drives i/o pins with the data word referenced by the input address. when either chip enable or output enable is inactive, or write enable is active, output drivers stay in high-impedance mode. these devices provide multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be written and read. lb controls the lower bits, i/o1Ci/o8, and ub controls the higher bits, i/o9Ci/o16. all chip inputs and outputs are ttl- and cmos-compatible, and operation is from either a single 5v (as7c4098) or 3.3v (AS7C34098) supply. both devices are available in the jedec standard 400-ml, 44-pin soj and tsop ii packages. absolute maximum ratings note: stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specificat i on is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. truth table key: x = dont care, l = low, h = high. parameter device symbol min max unit volt age on v cc relative to gnd as7c4098 v t1 C0.50 +7.0 v AS7C34098 v t1 C0.50 +5.0 v voltage on any pin relative to gnd v t2 C0.50 v cc +0.50 v power dissipation p d C1.5w storage temperature (plastic) t stg C65 +150 c ambient temperature with v cc applied t bias C55 +125 c dc current into outputs (low) i out C20ma ce we oe lb ub i/o1Ci/o8 i/o9Ci/o16 mode h x x x x high z high z standby (i sb , i sb1 ) lhhxx high z high z output disable (i cc ) lxxhh lhl lh d out high z read (i cc ) hl high z d out ll d out d out llx lh d in high z write (i cc ) hl high z d in ll d in d in
? as7c4098 AS7C34098 7/21/00 alliance semiconductor 3 recommended operating conditions dc operating characteristics (over the operating range) 1 shaded areas indicate preliminary information. capacitance (f = 1mhz, t a = 25 c, v cc = nominal) 2 parameter symbol min typical max unit supply voltage as7c4098 v cc (10/12/15/20) 4.5 5.0 5.5 v AS7C34098 v cc (C10) 3.15 3.3 3.6 v AS7C34098 v cc (10/12/15/20) 3.0 3.3 3.6 v input voltage as7c4098 v ih 2.2 C v cc + 0.5 v AS7C34098 v ih 2.0 C v cc + 0.5 v v il C0.5 * * v il min = C3.0v for pulse width less than t rc /2. C0.8v ambient operating temperature commercial t a 0C 70 c industrial t a C40 C 85 c parameter symbol test conditions C10 C12 C15 C20 unit min max min max min max min max input leakage current |i li | v cc = max v in = gnd to v cc C 1C 1 C1C1a output leakage current |i lo | v cc = max ce = v ih or oe = v ih or we = v il v i/o = gnd to v cc C 1C 1 C1C1a operating power supply current i cc v cc = max min cycle, 100% duty ce = v il , i out = 0ma as7c4098 C C C 250 C 220 C 180 ma AS7C34098 C 160 C 130 C 110 C 100 ma standby power supply current i sb v cc = max ce = v ih , f = max as7c4098 C C C 60 C 60 C 60 ma AS7C34098 C 60 C 60 C 60 C 60 ma i sb1 v cc = max ce 3 v cc C 0.2v, v in 3 v cc C 0.2v or v in 0.2v, f = 0 as7c4098 C C C 20 C 20 C 20 ma AS7C34098 C 20 C 20 C 20 C 20 ma output voltage v ol i ol = 8 ma, v cc = min C 0.4 C 0.4 C 0.4 C 0.4 v v oh i oh = C4 ma, v cc = min 2.4 C 2.4 C 2.4 C 2.4 C v parameter symbol signals test conditions max unit input capacitance c in a, ce , we , oe , ub , lb v in = 0v 6 pf i/o capacitance c i/o i/o v in = v out = 0v 8 pf
? 4 alliance semiconductor 7/21/00 as7c4098 AS7C34098 read cycle (over the operating range) 3,9 shaded areas indicate preliminary information. key to switching waveforms read waveform 1 (address controlled) 6,7,9 read waveform 2 (ce , oe , ub , lb controlled) 6,8,9 parameter symbol C10 C12 C15 C20 unit notes min max min max min max min max read cycle time t rc 10 C 12 C 15 C 20 C ns address access time t aa C 10 C 12 C 15 C 20 ns chip enable (ce ) access time t ace C 10 C 12 C 15 C 20 ns output enable (oe ) access time t oe C 5 C6C7C9ns output hold from address change t oh 3 C 3C3C3Cns5 ce low to output in low z t clz 0 C 3C0C0Cns4, 5 ce high to output in higfch z t chz C 5 C6C7C9ns4, 5 oe low to output in low z t olz 0 C 0C0C0Cns4, 5 oe high to output in high z t ohz C 5 C6C7C9ns4, 5 lb , ub access time t ba C 5 C6C7C9ns lb , ub low to output in low z t blz 0 C 0C0C0Cns lb , ub high to output in high z t bhz C 5 C6C7C9ns power up time t pu 0 C 0C0C0Cns5 power down time t pd C 10 C 12 C 15 C 20 ns 5 undefined/dont care falling input rising input t oh t aa t rc t oh data out address data valid previous data valid data valid t rc t aa t blz t ba t oe t olz t oh t ohz t chz t bhz t ace t lz address oe ce lb , ub data out
? as7c4098 AS7C34098 7/21/00 alliance semiconductor 5 write cycle (over the operating range) 11 shaded areas indicate prelimin ary information. write waveform 1(we controlled) 10,11 write waveform 2 (ce controlled) 10,11 parameter symbol C10 C12 C15 C20 unit note min max min max min max min max write cycle time t wc 10 C 12 C 15 C 20 C ns chip enable (ce ) to write end t cw 7 C 8 C 10 C 12 C ns address setup to write end t aw 7 C 8 C 10 C 12 C ns address setup time t as 0C0C0C0Cns write pulse width (oe = high) t wp1 7 C 8 C 10 C 12 C ns write pulse width (oe = low) t wp2 10 C 12 C 15 C 20 C ns address hold from end of write t ah 0C0C0C0Cns data valid to write end t dw 567C9Cns data hold time t dh 0C0C0C0Cns4, 5 write enable to output in high-z t wz 05060709ns4, 5 output active from write end t ow 3C3C3C3Cns4, 5 byte enable low to write end t bw 7 C 8 C 10 C 12 C ns 4, 5 address ce lb , ub we data in data out t wc t cw t bw t aw t as t wp t dw t dh t ow t wz t ah data undefined high z data valid address ce lb , ub we data in t wc t cw t bw t wp t dw t dh t ow t wz t ah data out data undefined high z high z t as t aw data valid t clz
? 6 alliance semiconductor 7/21/00 as7c4098 AS7C34098 write waveform 3 10,11 data retention characteristics 13 data retention waveform ac test conditions notes 1during v cc power-up, a pull-up resistor to v cc on ce is required to meet i sb specification. 2 this parameter is sampled, but not 100% tested. 3 for test conditions, see ac test conditions , figures a, b, c. 4t clz and t chz are specified with c l = 5pf as in figure c. transition is measured 500mv from steady-state voltage. 5 this parameter is guaranteed, but not tested. 6we is high for read cycle. 7ce and oe are low for read cycle. 8 address valid prior to or coincident with ce transition low. 9 all read cycle timings are referenced from the last valid address to the first transitioning address. 10 ce or we must be high during address transitions. either ce or we asserting high terminates a write cycle. 11 all write cycle timings are referenced from the last valid address to the first transitioning address. 12 not applicable. 13 2v data retention applies to commercial temperature range operation only. 14 c = 30pf, except on high z and low z parameters, where c = 5pf. parameter symbol test conditions min max unit v cc for data retention v dr v cc = 2.0v ce 3 v cc C 0.2v v in 3 v cc C 0.2v or v in 0.2v 2.0 C v data retention current i ccdr C500 m a chip deselect to data retention time t cdr 0Cns operation recovery time t r t rc Cns input leakage current |i li |C1 m a address ce lb , ub we data in t wc t cw t bw t wp t dw t dh t wz t ah data out data undefined high z high z t as t aw data valid v cc ce t r t cdr data retention mode v cc v cc v dr 3 2.0v v ih v ih v dr - output load: see figure b or figure c. - input pulse level: gnd to 3.0v. see figure a. - input rise and fall times: 2 ns. see figure a. - input and output timing reference levels: 1.5v. 10% 90% 10% 90% gnd +3.0v 2 ns figure a: input pulse 255w c(14) 480w d out gnd +5v figure b: 5v output load 350w c(14) 320w d out gnd +3.3v figure c: 3.3v output load 168w thevenin equivalent: d out +1.728v (5v and 3.3v)
? as7c4098 AS7C34098 7/21/00 alliance semiconductor 7 typical dc and ac characteristics 12 supply voltage (v) min max nominal 0.0 0.2 0.6 0.8 0.4 1.0 1.2 1.4 normalized i cc , i sb normalized supply current icc, isb ambient temperature ( c) C55 80 125 35 C10 0.0 0.2 0.6 0.8 0.4 1.0 1.2 1.4 normalized i cc , i sb normalized supply current i cc , i sb vs. ambient temperature t a vs. supply voltage vcc i cc i sb i cc i sb ambient temperature ( c) C55 80 125 35 C10 0.2 1 0.04 5 25 625 normalized isb1 (log scale) normalized supply current i sb1 vs. ambient temperature t a v cc = v cc (nominal) supply voltage (v) min max nominal 0.8 0.9 1.1 1.2 1.0 1.3 1.4 1.5 normalized access time normalized access time t aa ambient temperature ( c) C55 80 125 35 C10 0.8 0.9 1.1 1.2 1.0 1.3 1.4 1.5 normalized access time normalized access time t aa cycle frequency (mhz) 075 100 50 25 0.0 0.2 0.6 0.8 0.4 1.0 1.2 1.4 normalized i cc normalized supply current i cc vs. ambient temperature t a vs. cycle frequency 1/t rc , 1/t wc vs. supply voltage v cc v cc = v cc (nominal) t a = 25 c v cc = v cc (nominal) t a = 25 c output voltage (v) v cc 0 20 60 80 40 100 120 140 output source current (ma) output source current i oh output voltage (v) v cc output sink current (ma) output sink current i ol vs. output voltage v ol vs. output voltage v oh 0 20 60 80 40 100 120 140 v cc = v cc (nominal)pl t a = 25 c v cc = v cc (nominal) t a = 25 c capacitance (pf) 0 750 1000 500 250 0 5 15 20 10 25 30 35 change in t aa (ns) typical access time change d t aa vs. output capacitive loading v cc = v cc (nominal) 00
? 8 alliance semiconductor 7/21/00 as7c4098 AS7C34098 package dimensions ordering codes na : not available. part numbering system package version 10 ns 12 ns 15 ns 20 ns soj 5v commercial na as7c4098-12jc as7c4098-15jc as7c4098-20jc 5v industrial na as7c4098-12ji as7c4098-15ji as7c4098-20ji 3.3v commercial AS7C34098-10jc AS7C34098-12jc AS7C34098-15jc AS7C34098-20jc 3.3v industrial na AS7C34098-12ji AS7C34098-15ji AS7C34098-20ji tsop ii 5v commercial na as7c4098-12tc as7c4098-15tc as7c4098-20tc 5v industrial na as7c4098-12ti as7c4098-15ti as7c4098-20ti 3.3v commercial AS7C34098-10tc AS7C34098-12tc AS7C34098-15tc AS7C34098-20tc 3.3v industrial na AS7C34098-12ti AS7C34098-15ti AS7C34098-20ti as7c x 4098 Cxx j, t x sram prefix blank: 5v cmos 3: 3.3v cmos device number access time packages: j: soj 400 mil t: tsop ii 400 mil temperature ranges: c: commercial, 0c to 70c i: industrial, C40c to 85c 44-pin tsop ii min (mm) max (mm) a1.2 a 1 0.05 a 2 0.95 1.05 b 0.25 0.45 c 0.15 (typical) d 20.85 21.05 e 10.06 10.26 h e 11.56 11.96 e 0.80 (typical) l 0.40 0.60 d h e 123456789 1011121314 44 43424140393837363534333231 1516 3029 1718 1920 272625 c l a 1 a 2 e 44-pin tsop ii 0C5 21 24 22 23 e a b 44-pin soj 400 mil min max a 0.128 0.148 a1 0.025 - a2 1.105 1.115 b 0.026 0.032 b 0.015 0.020 c 0.007 0.013 d 1.120 1.130 e 0.370 nom e1 0.395 0.405 e2 0.435 0.445 e 0.050 nom seating plane 44-pin soj 28 pin 1 d e e2 e1 a1 b b a a2 e2 c
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